SH7205 Datasheet, PDF (1306/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Register
Name
Bit Name
DCPCTR ACLRM
PIPEnCTR SQCLR
SQSET
SQMON
PBUSY
PID
PIPEnTRE TRENB
TRCLR
PIPEnTRN TRNCNT
Setting
Contents
Remarks
Auto buffer clear PIPE1 to PIPE9: Can be set
Sequence clear Clears the data toggle bit
Sequence set Sets the data toggle bit
Sequence
monitor
Monitors the data toggle bit
Pipe busy status
Response PID
Transaction
PIPE1 to PIPE5: Can be set
counter enable
Current
transaction
counter clear
PIPE1 to PIPE5: Can be set
Transaction
counter
PIPE1 to PIPE5: Can be set
Rev. 1.00 Mar. 25, 2008 Page 1274 of 1868
REJ09B0372-0100