SH7205 Datasheet, PDF (1831/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 33 Electrical Characteristics
33.4.14 FLCTL Timing
Table 33.19 AND Type Flash Memory Interface Timing
Conditions: VCC = PLLVCC = 1.1 to 1.3 V, USBDVCC = 1.1 to 1.3 V, USBAVCC = 1.1 to 1.3 V,
PVCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V, USBAPVCC = 3.0 to 3.6 V,
2DGAPVCC0 = 3.0 to 3.6 V, 2DGAPVCC1 = 3.0 to 3.6 V,
VSS = PLLVSS = USBAVSS = AVSS = USBAPVSS = 2DGAPVSS0 = 2DGAPVSS1 = 0 V,
Ta = −20 to 85 °C
Item
Command issue setup time
Command issue hold time
Data output setup time
Data output hold time
Data output setup time 2
Data output hold time 2
FWE cycle time
FWE low pulse width
Symbol Min.
tACDS
2 × tfcyc − 10
tACDH
2 × tfcyc − 10
tADOS
tfcyc − 10
tADOH
tfcyc − 10
tADOS2
0.5 × tfcyc − 10
tADOH2
0.5 × tfcyc − 10
tACWC
2 × tfcyc − 5
tAWP
tfcyc − 5
FWE high pulse width
Command to address transition time
Address to data read transition time
Address to ready/busy transition time
Ready/busy to data read transition
time
Data read setup time
FSC cycle time
FSC high pulse width
FSC low pulse width
Read data setup time
Read data hold time
Status read setup time
tAWPH
tACAS
tAADDR
tAADRB
tARBDR
tADRS
tASCC
tASP
tASPL
tARDS
tARDH
tASRDS
tfcyc − 5
4 × tfcyc
32 × tpcyc

3 × tfcyc
tfcyc − 10
tfcyc − 5
0.5 × tfcyc − 5
0.5 × tfcyc − 5
24
5
2 × tpcyc + 24
Max. Unit Figure

ns Figures 33.44,

ns ^33.48

ns Figures 33.44,

ns ^{33.45, 33.48}

ns Figure 33.47

ns

ns Figure 33.45

ns Figures 33.44,
33.45, 33.48

ns Figure 33.45

ns

ns Figure 33.46
35 × tpcyc ns

ns

ns Figure 33.46

ns Figures 33.46,

ns ^33.47

ns

ns Figures 33.46,

ns ^33.48

ns Figure 33.48
Rev. 1.00 Mar. 25, 2008 Page 1799 of 1868
REJ09B0372-0100