SH7205 Datasheet, PDF (878/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 18 I²C Bus Interface 3 (IIC3)
Bit
5
4
3 to 0
Bit Name
MST
TRS
Initial
Value
0
0
CKS[3:0] 0000
R/W Description
R/W Master/Slave Select
R/W Transmit/Receive Select
In master mode with the I²C bus format, when
arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode.
Modification of the TRS bit should be made between
transfer frames.
When seven bits after the start condition is issued in
slave receive mode match the slave address set to
SAR and the 8th bit is set to 1, TRS is automatically
set to 1. If an overrun error occurs in master receive
mode with the clocked synchronous serial format, MST
is cleared and the mode changes to slave receive
mode.
Operating modes are described below according to
MST and TRS combination. When clocked
synchronous serial format is selected and MST = 1,
clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
R/W Transfer Clock Select
These bits should be set according to the necessary
transfer rate (table 18.3) in master mode.
Rev. 1.00 Mar. 25, 2008 Page 846 of 1868
REJ09B0372-0100