SH7205 Datasheet, PDF (1628/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 31 User Debugging Interface (H-UDI)
31.5.2 Reset Configuration
Table 31.7 Reset Configuration
ASEMD*¹ RES
TRST
Chip State
H
L
L
Power-on reset and H-UDI reset
H
Power-on reset
H
L
H-UDI reset only
H
Normal operation
L
L
L
Reset hold*²
H
Power-on reset
H
L
H-UDI reset only
H
Normal operation
Notes: 1. Performs product chip mode and ASE mode settings
ASEMD = H, normal mode
ASEMD = L, ASE mode
2. In ASE mode, reset hold is entered if the TRST pin is driven low while the RES pin is
negated. In this state, the CPU does not start up. When TRST is driven high, H-UDI
operation is enabled, but the CPU does not start up. The reset hold state is cancelled
by a power-on reset.
31.5.3 TDO Output Timing
When the emulation TAP controller is selected, a transition on the TDO pin is output on the
falling edge of TCK with the initial value. However, setting a TDO transition timing switching
command in SDIR via the H-UDI pin and passing the Update-IR state synchronizes the TDO
transition with the rising edge of TCK. This command does not affect the output timing of the
boundary scan TAP controller.
To synchronize the transition of TDO with the falling edge of TCK after setting the TDO
transition timing switching command, the TRST pin must be asserted simultaneously with the
power-on reset. In the case of power-on reset by the RES pin, the sync reset is still in operation for
a certain period in the LSI even after the RES pin is negated. Thus, if the TRST pin is asserted
immediately after the negation of the RES pin, the TDO transition timing switching command is
cleared, resulting in TDO transitions synchronized with the falling edges of TCK. To prevent this,
make sure to allow a period of 20 tcyc or longer between the signal transitions of the RES and
TRST pins.
Rev. 1.00 Mar. 25, 2008 Page 1596 of 1868
REJ09B0372-0100