SH7205 Datasheet, PDF (453/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.26 DMA Reload Two-Dimensional Addressing Next Block Offset Register
(DMR2DNBOSTm)
DMR2DNBOSTm is a register used to set the offset to be reloaded to the DMA two-dimensional
addressing next block offset register (DM2DNBOSTm). To enable the reload function, set the
two-dimensional reload function enable bit (2DRLOD) of DMA control register A (DMCNTAm)
to 1. When enabled, it is necessary to set both the DMA two-dimensional addressing next block
offset register (DM2DNBOSTm) and DMA reload two-dimensional addressing next block offset
register (DMR2DNBOSTm).
Bit: 31
Initial value: -
R/W: R/W
30
-
R/W
29
-
R/W
28
-
R/W
27
-
R/W
26
-
R/W
25 24 23 22
DRNBOST[31:16]
-
-
-
-
R/W R/W R/W R/W
21
-
R/W
20
-
R/W
19
-
R/W
18
-
R/W
17
-
R/W
16
-
R/W
Bit: 15
Initial value: -
R/W: R/W
14
-
R/W
13
-
R/W
12
-
R/W
11
-
R/W
10
-
R/W
9
8
7
6
DRNBOST[15:0]
-
-
-
-
R/W R/W R/W R/W
5
-
R/W
4
-
R/W
3
-
R/W
2
-
R/W
1
-
R/W
0
-
R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 0
DRNBOST
[31:0]
Undefined
R/W DMA Next Block Offset Byte Count for Reloading
These bits are used to set the number of offset bytes to
be reloaded to the DMA two-dimensional addressing next
block offset register. Set a two’s complement number in
these bits.
Rev. 1.00 Mar. 25, 2008 Page 421 of 1868
REJ09B0372-0100