SH7205 Datasheet, PDF (1308/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
24.4.4 FIFO Buffer
This section describes the operation related to the FIFO buffer in the USB module. Unless
otherwise noted, the operation is the same regardless of whether the host controller or function
controller function is selected.
(1) FIFO Buffer Allocation
Figure 24.9 shows an example of FIFO buffer mapping of this module. The FIFO buffer is an area
shared by the CPU and this module. As the FIFO buffer statuses, there is a state in which the
access right to the FIFO buffer is held by the system (CPU side), and a state in which the access
right is held by this module (SIE side).
Areas for the FIFO buffer are set independently for each pipe. A memory area is set by specifying
the first block number and the number of blocks, where one block consists of 64 bytes (the
settings are made through the BUFNMB and BUFSIZE bits in PIPEBUF). When continuous
transfer mode has been selected using the CNTMD bit in PIPEnCFG, the BUFSIZE bits should be
set so that the buffer memory size should be an integral multiple of the maximum packet size.
When double buffer mode has been selected using the DBLB bit in PIPEnCFG, two planes of the
memory area specified using the BUFSIZE bits in PIPEBUF can be assigned to a single pipe.
Three FIFO ports are used for access to the FIFO buffer (reading and writing data). A pipe is
assigned to the FIFO port by specifying the pipe number using the CURPIPE bit in
C/DnFIFOSEL.
The FIFO buffer statuses of the various pipes can be confirmed using the BSTS bit in DCPCTR
and the INBUFM bit in PIPEnCTR. Also, the access right of the FIFO port can be confirmed
using the FRDY bit in C/DnFIFOCTR.
Rev. 1.00 Mar. 25, 2008 Page 1276 of 1868
REJ09B0372-0100