SH7205 Datasheet, PDF (1447/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
SA buffer
GR_BRDCOL register
(Color value = Ca) (Color value = BRDC_X)
(α value = αa)
GR_BRD1CNT register
GCOLR bit = (0/1)
Output data of the 4-to-1 selection
(Color value = Cb1)
(α value = αb)
1
0
Ca1 αa
(1) Selection of SA data
Cb1 αb
Fa
Fb
FBFA bit in the
GR_BRD1CNT register
(2) Blending
Cout = Fb × Cb1 + Fa × Ca1
αout = (Determined by the FBFA bit in the
GR_BRDICNT register)
(3) Selection of α value
1
0
Cdc = Cout
αdc
DC output data (Color value = Cdc, α value = αdc)
AFTER_A bit in the
GR_BRD1CNT register
GALFA bit in the
GR_BRD1CNT register
= (0/1)
Figure 26.23 Summary of Blitter Operations during Blending
Rev. 1.00 Mar. 25, 2008 Page 1415 of 1868
REJ09B0372-0100