SH7205 Datasheet, PDF (1780/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 32 List of Registers
32.3 Register States in Each Operating Mode
Module Register
Power-On Manual Deep
Software Module
Name Abbreviation Reset
Reset
Standby Standby Standby
Multi-core All registers
processor
CPG
FRQCR0
Initialized Retained Initialized Retained 
Initialized*¹ Retained Initialized Retained 
INTC
FRQCR1
IBNR
Initialized*¹ Retained Initialized Retained 
Initialized Retained*² Initialized Retained 
Other than
above
Initialized Retained Initialized Retained 
UBC
All registers Initialized Retained Initialized Retained Retained
Cache All registers Initialized Retained Initialized Retained 
BSC
All registers Initialized Retained Initialized Retained 
DMAC All registers Initialized Retained Initialized Retained 
MTU2 All registers Initialized Retained Initialized Retained Initialized
CMT
All registers Initialized Retained Initialized Initialized Retained
WDT WTCSR0
Initialized Retained Initialized Retained 
WTCNT0
WRCSR0
Initialized Retained Initialized Retained 
Initialized*¹ Retained Initialized Retained 
WTCSR1
Initialized Retained Initialized Retained 
WTCNT1
Initialized Retained Initialized Retained 
RTC
WRCSR1
R64CNT
Initialized*¹ Retained Initialized Retained 
Retained*³ Retained*³ Retained*³ Retained*³ Retained
RSECCNT
RMINCNT
RHRCNT
RWKCNT
RDAYCNT
RMONCNT
RYRCNT
RSECAR
Initialized Retained Initialized Retained Retained
RMINAR
Sleep
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained*³
Retained
Rev. 1.00 Mar. 25, 2008 Page 1748 of 1868
REJ09B0372-0100