SH7205 Datasheet, PDF (178/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Exception Handling
6.3.2 Address Error Exception Handling
When an address error occurs, the bus cycle in which the address error occurred ends*, the
executing instruction finishes, and address error exception handling starts. The CPU operates as
follows:
1. The exception service routine start address which corresponds to the address error that
occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction.
4. After jumping to the address fetched from the exception handling vector table, program
execution starts. The jump that occurs is not a delayed branch.
Note: * In the case of an address error caused by instruction fetching when data is read or
written, if the bus cycle on which the address error occurred is not completed by the
end of the operations described above, the CPU will recommence address error
exception processing until the end of that bus cycle.
Rev. 1.00 Mar. 25, 2008 Page 146 of 1868
REJ09B0372-0100