SH7205 Datasheet, PDF (818/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
16.4.3 Operation in Clock Synchronous Mode
In clock synchronous mode, the SCIF transmits and receives data in synchronization with clock
pulses. This mode is suitable for high-speed serial communication.
The SCIF transmitter and receiver are independent, so full-duplex communication is possible
while sharing the same clock. The transmitter and receiver are also 16-byte FIFO buffered, so
continuous transmitting or receiving is possible by reading or writing data while transmitting or
receiving is in progress.
Figure 16.11 shows the general format in clock synchronous serial communication.
*
Serial clock
One unit of transfer data (character or frame)
*
LSB
Serial data Don't care Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
MSB
Bit 7
Don't care
Note: * High except in continuous transfer
Figure 16.11 Data Format in Clock Synchronous Communication
In clock synchronous serial communication, each data bit is output on the communication line
from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of
the serial clock.
In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB
(last). After output of the MSB, the communication line remains in the state of the MSB.
In clock synchronous mode, the SCIF receives data by synchronizing with the rising edge of the
serial clock.
Rev. 1.00 Mar. 25, 2008 Page 786 of 1868
REJ09B0372-0100