SH7205 Datasheet, PDF (364/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Reset
Initialization sequence:
(1) Set DPC, DARFC, and DARFI bits in SDIR0
(2) Set DINIRQ bit in SDIR1 to 1
(3) Wait for DINIST bit in SDIR1 to be cleared to 0
Channel i settings:
(1) Confirm that all status bits in SDSTR have been cleared to 0
(2) Set SDmMOD mode register
(3) Set DRAS, DRCD, DPCG, DCL, and DWR bits in SDmTR
(4) Set DSZ bits in SDmADR
Make settings for
all channels to be used
Start auto-refreshing:
Set DRFEN bit in SDRFCNT1 to 1
Enable access:
Set SDRAMCm control register to enable operation
SDRAM access enabled
Figure 10.25 (a) SDRAMC Setting Procedure (Basic Setting Example)
Rev. 1.00 Mar. 25, 2008 Page 332 of 1868
REJ09B0372-0100