SH7205 Datasheet, PDF (1127/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
23.3.12 Control Code FIFO Register (FLECFIFO)
FLECFIFO is used to read or write the control code FIFO area.
In DMA transfer, data in this register must be specified as the destination (source).
Note that the direction of read or write specified by the SELRW bit in FLCMDCR must match
that specified in this register. When changing the read/write direction, FLECFIFO should be
cleared by setting the AC1CLR bit in FLINTDMACR before use.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECFO[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
ECFO[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Initial
Bit Name Value
R/W Description
ECFO[31:0] H'xxxxxxxx R/W Control Code FIFO Area Read/Write Data
In write: Data in this register is written to the control
code FIFO area.
In read: Data read from the control code FIFO area is
stored in this register.
Rev. 1.00 Mar. 25, 2008 Page 1095 of 1868
REJ09B0372-0100