SH7205 Datasheet, PDF (715/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 14 Watchdog Timer (WDT)
Section 14 Watchdog Timer (WDT)
This LSI includes the watchdog timer (WDT), which externally outputs an overflow signal
(WDTOVF) on overflow of the counter when the value of the counter has not been updated
because of a system malfunction. The WDT can simultaneously generate an internal reset signal
for the entire LSI.
The WDT is a single channel timer for each of CPU0 and CPU1, and WDT0 for CPU0 counts up
the clock oscillation settling period when the system leaves software standby mode or the
temporary standby periods that occur when the clock frequency is changed. Both WDT0 and
WDT1 can be used as a general watchdog timer or interval timer.
14.1 Features
• Can be used to ensure the clock oscillation settling time (WDT0)
The WDT is used in leaving software standby mode or the temporary standby periods that
occur when the clock frequency is changed.
• Can switch between watchdog timer mode and interval timer mode (WDT0, WDT1)
• Outputs WDTOVF signal in watchdog timer mode (WDT0, WDT1)
When the counter overflows in watchdog timer mode, the WDTOVF signal is output
externally. It is possible to select whether to reset the LSI internally when this happens. Either
the power-on reset or manual reset signal can be selected as the internal reset type.
• Issues an interrupt in interval timer mode (WDT0, WDT1)
An interval timer interrupt is issued when the counter overflows.
• Can select one of eight counter input clocks (WDT0, WDT1)
Eight clocks (Pφ × 1 to Pφ × 1/16384) that are obtained by dividing the peripheral clock can be
selected.
Rev. 1.00 Mar. 25, 2008 Page 683 of 1868
REJ09B0372-0100