SH7205 Datasheet, PDF (1000/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 Controller Area Network (RCAN-TL1)
Bit 7 - Overload Frame (IRR7): Flag indicating that the RCAN-TL1 has detected a condition
that should initiate the transmission of an overload frame. Note that in the condition of
transmission being prevented, such as listen only mode, an Overload Frame will NOT be
transmitted, but IRR7 will still be set. IRR7 remains asserted until reset by writing a ‘1’ to this bit
position - writing a ‘0’ has no effect.
Bit 7: IRR7
0
1
Description
[Clearing condition] Writing 1 (Initial value)
[Setting conditions] Overload condition detected
Bit 6 - Bus Off Interrupt Flag (IRR6): This bit is set when RCAN-TL1 enters the Bus-off state
or when RCAN-TL1 leaves Bus-off and returns to Error-Active. The cause therefore is the
existing condition TEC ≥ 256 at the node or the end of the Bus-off recovery sequence (128X11
consecutive recessive bits) or the transition from Bus Off to Halt (automatic or manual). This bit
remains set even if the RCAN-TL1 node leaves the bus-off condition, and needs to be explicitly
cleared by S/W. The S/W is expected to read the GSR0 to judge whether RCAN-TL1 is in the bus-
off or error active status. It is cleared by writing a ‘1’ to this bit position even if the node is still
bus-off. Writing a ‘0’ has no effect.
Bit 6: IRR6
0
1
Description
[Clearing condition] Writing 1 (Initial value)
Enter Bus off state caused by transmit error or Error Active state returning
from Bus-off
[Setting condition]
When TEC becomes ≥ 256 or End of Bus-off after 128X11 consecutive
recessive bits or transition from Bus Off to Halt
Bit 5 - Error Passive Interrupt Flag (IRR5): Interrupt flag indicating the error passive state
caused by the transmit or receive error counter or by Error Passive forced by test mode. This bit is
reset by writing a ‘1’ to this bit position, writing a ‘0’ has no effect. If this bit is cleared the node
may still be error passive. Please note that the SW needs to check GSR0 and GSR5 to judge
whether RCAN-TL1 is in Error Passive or Bus Off status.
Bit 5: IRR5
0
1
Description
[Clearing condition] Writing 1 (Initial value)
Error passive state caused by transmit/receive error
[Setting condition]
When TEC ≥ 128 or REC ≥ 128 or Error Passive test mode is used
Rev. 1.00 Mar. 25, 2008 Page 968 of 1868
REJ09B0372-0100