SH7205 Datasheet, PDF (300/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Internal Address
Space Memory to be Connected
BIU*¹
Size Cache
H'F0000000 to H'F1FFFFFF Others Cache address array space or other *²
H'F2000000 to H'FEFFFFFF Reserved Reserved area


Cache-

disabled
H'FF400000 to H'FF7FFFFF Others
On-chip peripheral modules, reserved BIU_PB2 4MB
area
H'FF800000 to H'FF9FFFFF Others
On-chip peripheral modules, on-chip BIU_PB0 2MB
RAM for data retention, reserved area
H'FFA00000 to H'FFBFFFFF Others
On-chip peripheral modules, reserved BIU_PB1 2MB
area
H'FFC00000 to H'FFD7FFFF Reserved Reserved area


H'FFD80000 to H'FFD8FFFF On-chip On-chip high-speed RAM0 space
RAM0 (shadow)
BIU_PB0 64KB
H'FFD90000 to H'FFD9FFFF Reserved Reserved area


H'FFDA0000 to H'FFDA7FFF On-chip On-chip high-speed RAM1 space
RAM1 (shadow)
BIU_PB1 32KB
H'FFDA8000 to H'FFF7FFFF Reserved Reserved area


H'FFF80000 to H'FFF8FFFF On-chip On-chip high-speed RAM0 space
RAM0
BIU_PB0 64KB
H'FFF90000 to H'FFF9FFFF Reserved Reserved area


H'FFFA0000 to H'FFFA7FFF On-chip On-chip high-speed RAM1 space
RAM1
BIU_PB1 32KB
H'FFFA8000 to H'FFFBFFFF Reserved Reserved area


H'FFFC0000 to H'FFFCFFFF Others
On-chip peripheral modules, reserved *²
area
64KB
H'FFFD0000 to H'FFFEFFFF Others
On-chip peripheral modules, reserved BIU_PB0 128KB
area
H'FFFF0000 to H'FFFFFFFF Others
On-chip peripheral modules, reserved BIU_PB1 64KB
area
Notes: 1. The term BIU stands for Bus Interface Unit. BIUs are internal modules through which
the CPU and DMAC accesses each address space. Described below are on-chip BIUs,
and address spaces and internal buses connected to these BIUs.
BIU_E: External address spaces (normal and SDRAM spaces)
BIU_PB0: peripheral bus 0 (internal to the LSI)
BIU_PB1: peripheral bus 1 (internal to the LSI)
BIU_PB2: peripheral bus 2 (internal to the LSI)
BIU_PB3: peripheral bus 3 (internal to the LSI)
Pipelined DMA transfer is not available for transfer from a BIU to the same BIU. For
details, see section 11, Direct Memory Access Controller (DMAC).
2. Cache address array space and some on-chip peripheral modules are not allocated to
any BIU. These devices are accessed directly from individual CPUs without using the
system bus. The DMAC cannot access any of these devices.
Rev. 1.00 Mar. 25, 2008 Page 268 of 1868
REJ09B0372-0100