SH7205 Datasheet, PDF (238/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.6 Operation
7.6.1 Interrupt Operation Sequence
The interrupt operation sequence is described below. Figure 7.2 shows the operation flow.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest-priority interrupt from the sent interrupt requests,
according to the priority levels set in interrupt priority registers 01, 02, and 05 to 21 (C0IPR01,
C0IPR02, and C0IPR05 to C0IPR21 and C1IPR01, C1IPR02, and C1IPR05 to C1IPR21).
Lower priority interrupts are ignored*. If two of more interrupts have the same priority level or
if two or more interrupts specified by the same IPR setting occur, the interrupt with the highest
priority is selected, according to the default priorities shown in table 7.8.
3. The priority level of the interrupt selected by the interrupt controller is compared with the
interrupt mask level bits (I3 to I0) in the status register (SR) of the CPU. If the priority level is
equal to or lower than the level set in bits I3 to I0, the interrupt is ignored. Only when the
priority level is higher than the level in bits I3 to I0, the interrupt controller accepts the
interrupt and sends an interrupt request signal to the CPU.
4. The CPU detects the interrupt request sent from the interrupt controller when the CPU decodes
the instruction to be executed. Instead of executing the decoded instruction, the CPU starts
interrupt exception handling (figure 7.4).
5. The exception service routine start address is fetched from the exception handling vector table
corresponding to the accepted interrupt.
6. The status register (SR) is saved onto the stack, and the priority level of the accepted interrupt
is written to bits I3 to I0 in the SR.
7. The program counter (PC) is saved onto the stack.
8. The CPU jumps to the fetched exception service routine start address and starts executing the
program. The jump that occurs is not a delayed branch.
Notes: The interrupt source flag should be cleared in the interrupt handler. After clearing the
interrupt source flag, "time from occurrence of interrupt request until interrupt controller
identifies priority, compares it with mask bits in the SR, and sends interrupt request signal
to CPU" shown in table 7.9 is required before the interrupt source sent to the CPU is
actually cancelled. To ensure that an interrupt request that should have been cleared is not
inadvertently accepted again, read the interrupt source flag after it has been cleared, and
then execute an RTE instruction.
Rev. 1.00 Mar. 25, 2008 Page 206 of 1868
REJ09B0372-0100