SH7205 Datasheet, PDF (1030/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 Controller Area Network (RCAN-TL1)
Timer Clear-Set:
The Timer value can only be cleared when a Compare Match occurs if it is enabled by the Bit6 in
the TTCR0. TCMR1 and TCMR2 do not have this function.
Cancellation of the messages in the transmission queue:
The messages in the transmission queue can only be cleared by the TCMR2 through setting TXCR
when a Compare Match occurs while RCAN-TL1 is not in the halt status. TCMR1 and TCMR0 do
not have this function.
• TCMR0 (Address = H'098)
Bit:
Initial value:
R/W:
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
7
TCMR0[15:0]
1
1
R/W R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Bit 15 to 0 — Timer Compare Match Register (TCMR0): Indicates the value of TCNTR when
compare match occurs.
• TCMR1 (Address = H'09C)
Bit: 15
Initial value: 1
R/W: R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
7
TCMR1[15:0]
1
1
R/W R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Bit 15 to 0 — Timer Compare Match Register (TCMR1): Indicates the value of CYCTR when
compare match occurs.
• TCMR2 (Address = H'0A0)
Bit:
Initial value:
R/W:
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
7
TCMR2[15:0]
1
1
R/W R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
Rev. 1.00 Mar. 25, 2008 Page 998 of 1868
REJ09B0372-0100