SH7205 Datasheet, PDF (1499/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
(2) When the interrupt source is a completion of a blit operation, input of a VSYNC signal
for the output block, and output underflow for the output block, or capture of a last
line by the output block
(2-1) An interrupt event occurs in the 2DG.
(2-2) The INT_∗∗∗ bit in the interrupt status register for graphics (GR_IRSTST) is set accordingly
(interrupt signal = negative logic).
(2-3) The CPU recognizes the interrupt and reads the GR_IRSTAT register.
(2-4) The CPU writes 1 to the interrupt reset control register for graphics (GR_INTDIS).
(2-5) The IRQ_∗∗∗ bit in the GR_IRSTAT register is cleared in response to the above step (thus
deasserting the interrupt signal).
Figure 26.58 shows the interrupt processing flow.
SB_STEN
Interrupt event setting pulse
The INT_GR bits of
the GR_IRSTAT register
The DS_GR bits of
the GR_INTDIS register
Interrupt signal (negative logic)
An interrupt event occurs (2-1)
(2-2)
(2-2)
(2-5)
(2-4)
(2-5)
CPU operation
Recognizes the occurrence Reads from the
Writes to the interrupt reset
of an interrupt (2-3) interrupt status register (2-3) control register (2-4)
Figure 26.58 Interrupt Handling (2)
The 2DG interrupt signals are level-sensitive and more than one status bit is assigned to each
interrupt signal. Because of this, it is necessary for the CPU to read the interrupt status register
until the relevant interrupt signal is reset so that the CPU should recognize all the corresponding
status bits and handle them according to the specified priority.
Rev. 1.00 Mar. 25, 2008 Page 1467 of 1868
REJ09B0372-0100