SH7205 Datasheet, PDF (640/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.5 Interrupt Sources
12.5.1 Interrupt Sources and Priorities
There are three kinds of MTU2 interrupt source; TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled
bit, allowing the generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, however the priority order
within a channel is fixed. For details, see section 7, Interrupt Controller (INTC).
Table 12.55 lists the MTU2 interrupt sources.
Table 12.55 MTU2 Interrupts
Channel
0
1
2
Name Interrupt Source
TGIA_0 TGRA_0 input capture/compare match
TGIB_0 TGRB_0 input capture/compare match
TGIC_0 TGRC_0 input capture/compare match
TGID_0 TGRD_0 input capture/compare match
TCIV_0 TCNT_0 overflow
TGIE_0 TGRE_0 compare match
TGIF_0 TGRF_0 compare match
TGIA_1 TGRA_1 input capture/compare match
TGIB_1 TGRB_1 input capture/compare match
TCIV_1 TCNT_1 overflow
TCIU_1 TCNT_1 underflow
TGIA_2 TGRA_2 input capture/compare match
TGIB_2 TGRB_2 input capture/compare match
TCIV_2 TCNT_2 overflow
TCIU_2 TCNT_2 underflow
Interrupt DMAC
Flag
Activation
TGFA_0 Possible
TGFB_0 Not possible
TGFC_0 Not possible
TGFD_0 Not possible
TCFV_0 Not possible
TGFE_0 Not possible
TGFF_0 Not possible
TGFA_1 Possible
TGFB_1 Not possible
TCFV_1 Not possible
TCFU_1 Not possible
TGFA_2 Possible
TGFB_2 Not possible
TCFV_2 Not possible
TCFU_2 Not possible
Priority
High
Low
Rev. 1.00 Mar. 25, 2008 Page 608 of 1868
REJ09B0372-0100