SH7205 Datasheet, PDF (857/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 Synchronous Serial Communication Unit (SSU)
(3) Data Reception
Figure 17.7 shows an example of reception operation, and figure 17.8 shows a flowchart example
of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a low
level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU receives
data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit in SSER is set to 1, an SSRXI interrupt is generated.
The RDRF bit is automatically cleared to 0 by reading SSRDR.
In continuous reception as the slave device in SSU mode, be sure to read the SS receive data
register (SSRDR) before reception of the next frame starts (before the externally connected master
device starts the next transmission). If reception of a next frame starts while the receive data full
(RDRF) bit in the SS status register (SSSR) is set (to 1) because SSRDR has not yet been read,
and SSRDR is then read before reception of the next frame is complete, the conflict/incomplete
error (CE) bit in SSRDR will be set at the end of reception of the next frame. Furthermore, if
reception of a next frame starts after RDRF has been set (to 1) but before SSRDR has been read,
and SSRDR still has not been read by the end of reception of the next frame, neither the CE nor
the overrun error (ORER) bit in SSSR will be set, but the received data will be discarded.
Rev. 1.00 Mar. 25, 2008 Page 825 of 1868
REJ09B0372-0100