SH7205 Datasheet, PDF (33/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 1 Overview
Section 1 Overview
1.1 SH7205 Features
This LSI is a single-chip RISC (reduced instruction set computer) microcontroller that includes
two Renesas Technology-original RISC CPUs as its cores, and the peripheral functions required to
configure a system.
This LSI features a multi-processor architecture, that is, a dual-core architecture that includes two
units of SH-2A CPU, which provides upward compatibility for SH-1, SH-2, and SH-2E CPUs at
object code level. The SH-2A CPU has a RISC-type instruction set and uses a superscalar
architecture and a Harvard architecture, which greatly improves instruction execution speed. In
addition, the 32-bit internal-bus architecture that is independent from the direct memory access
controller (DMAC) enhances data processing power. This CPU brings the user the ability to set up
high-performance systems with strong functionality at less expense than was achievable with
previous microcontrollers, and is even able to handle realtime control applications requiring high-
speed characteristics.
This LSI includes a floating-point unit (FPU) and cache for each of the CPU cores (CPU0 and
CPU1). In addition, this LSI has on-chip peripheral functions necessary for system configuration:
64-Kbyte (CPU0) and 32-Kbyte (CPU1) RAM for high-speed operation, 16-Kbyte RAM for data
retention, an interrupt controller (INTC), a multi-function timer pulse unit 2 (MTU2), a compare
match timer (CMT), a realtime clock (RTC), a serial communication interface with FIFO (SCIF),
a synchronous serial communication unit (SSU), an I²C bus interface 3 (IIC3), a serial sound
interface with FIFO (SSIF), a controller area network (RCAN-TL1), an A/D converter (ADC), a
D/A converter (DAC), an AND/NAND flash memory controller (FLCTL), a USB2.0
host/function module supporting two ports (USB), an AT attachment packet interface (ATAPI), a
2D engine (2DG), and I/O ports.
This LSI also provides an external memory access support function to enable direct connection to
various memory devices or peripheral LSIs. These on-chip functions significantly reduce costs of
designing and manufacturing application systems. Furthermore, I/O pins in this LSI have weak
keeper circuits that prevent the pin voltage from entering an intermediate potential range.
Therefore, no external circuits for fixing the input level are required, which reduces the number of
parts considerably.
The features of this LSI are listed in table 1.1.
Rev. 1.00 Mar. 25, 2008 Page 1 of 1868
REJ09B0372-0100