SH7205 Datasheet, PDF (330/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
10.4.16 SDRAM Status Register (SDSTR)
SDSTR consists of the status flags that indicate the status of operation during self-refresh,
initialization sequences, power-down mode, deep-power-down mode, and mode register setting.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
- DSRFST DINIST DPWDST DDPDST DMRSST
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
31 to 5
Initial
Bit Name Value

All 0
4
DSRFST 0
3
DINIST 0
2
DPWDST 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R Self-Refresh Transition/Recovery Status
When set to 1, this bit indicates that a transition to or
recovery from self-refresh operation is in progress for the
channel for SDRAM0 or SDRAM1.
0: Transition/recovery not in progress
1: Transition/recovery in progress
R Initialization Status
When set to 1, this bit indicates that an SDRAM
initialization sequence is in progress for the channel for
SDRAM0 or SDRAM1. This bit has the same function as
the DINIST bit in the SDIR1 register.
0: Initialization sequence not in progress
1: Initialization sequence in progress
R Power-Down Transition/Recovery Status
When set to 1, this bit indicates that a transition to or
recovery from power-down mode is in progress on the
channel for SDRAM0 or SDRAM1.
0: Transition/recovery not in progress
1: Transition/recovery in progress
Rev. 1.00 Mar. 25, 2008 Page 298 of 1868
REJ09B0372-0100