SH7205 Datasheet, PDF (1433/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
26.4.2 How to Use the DMA
• The 2DG DMAC has four channels. DMAC allocate the channels according to the priority
level shown below:
SE buffer DMA (2DG output) > DC buffer DMA (2DG BLT output C) > SB buffer DMA
(2DG BLT input B) > SA buffer DMA (2DG BLT input A)
Examples of allocation are as follows:
Channel 1: SE buffer DMA
Channel 2: DC buffer DMA
Channel 3: SB buffer DMA
Channel 4: SA buffer DMA
• When performing a data transfer using the normal CPU transfer instead of the DMAC, set the
applicable DMx_MSEL bits of the GR_DMAC register to 11. Note that changing the transfer
method to a CPU transfer during a DMA transfer is prohibited.
• For the SA/SB areas, the same DMA setting can be effected by setting the DM34_DSEL and
DM34_MSEL bits of the GR_DMAC register.
• The number of bits (32 or 16) per data item is specified in terms of SZSEL1 (blitter)/SZSEL2
(output block). When the lower 2-bit addresses of the starting pixel for the DMA transfer are
not "00", clear SZSEL1 and SZSEL2 to 0 (16 bits).
• When SZSEL1 = 32 bits, SSWIDH is always set to an even number; for SZSEL1 = 16 bits,
SSWIDH can be either odd or even. Similarly, for SZSEL2 = 32 bits, SEWIDH is always
even, and when SZSEL2 = 16 bits, SEWIDH can be either odd or even. Even when the data
width of the SDRAM, which is external memory, is 16 bits, it is recommended to set the size
to 32 bits when the efficiency of data transfer is important. Basically, use 32 bits if one transfer
line = even pixels, and use 16 bits if one transfer line = odd pixels.
• Set the number of data items per operand so that the size of the buffer to be accessed is evenly
divisible.
For example, if data transfer size = 16 or 32 bits and one operand = 1, 2, 4, or 16 data items,
full image transfer (480 pixels) can be made to all buffers. However, if data transfer size = 32
bits and one operand = 32 data items, a full pixel (480 pixels) transfer to the SE buffer results
in 480/(32 × 2) = 7.5, the DMA transfer cannot be stopped at 240th word after performing
operand transfers seven times (access up to 32 × 7 = 224 words), which means that transfers
must be made up to the 256th word. In this case, if one operand = 16 data items, a full image
transfer can be made by performing operand transfers 15 times.
• When performing DMA access to the 2DG, set the first address of the buffer as the access-start
address. Starting DMA access beginning with a middle address is prohibited.
Rev. 1.00 Mar. 25, 2008 Page 1401 of 1868
REJ09B0372-0100