SH7205 Datasheet, PDF (817/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Figure 16.9 shows an example of the operation for reception.
Serial
data
Start
1 _bit
0 D0
Data
Parity Stop Start
bit bit bit
D1
D7 0/1 1
0 D0
Data
Parity Stop
bit
bit
1
D1
D7
0/1 1
Idle state
(mark state)
RDF
FER
RXI interrupt
request
One frame
Data read and RDF flag
read as 1 then cleared to 0
by RXI interrupt handler
ERI interrupt request
generated by receive
error
Figure 16.9 Example of SCIF Receive Operation
(8-Bit Data, Parity, 1 Stop Bit)
5. When modem control is enabled in channel 0, the RTS signal is output when SCFRDR is
empty. When RTS is 0, reception is possible. When RTS is 1, this indicates that SCFRDR
exceeds the number set for the RTS output active trigger.
Figure 16.10 shows an example of the operation when modem control is used.
Serial data
RxD
Start
bit
0 D0 D1 D2
Parity
bit
D7 0/1 1
Start
bit
0 D0 D1
D7 D1
RTS
Figure 16.10 Example of Operation Using Modem Control (RTS)
Rev. 1.00 Mar. 25, 2008 Page 785 of 1868
REJ09B0372-0100