SH7205 Datasheet, PDF (291/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Cache
(2) Address-Array Write (Non-Associative Operation)
When writing 0 to the associative bit (A bit) in the address field, the tag address, LRU bits, U bit
(only for operand cache), and V bit, specified by the data field, is written to the entry address
specified by the address and the entry corresponding to the way. When writing to a cache line for
which the U bit = 1 and the V bit =1 in the operand cache address array, write the contents of the
cache line back to memory, then write the tag address, LRU bits, U bit, and V bit specified by the
data field. When 0 is written to the V bit, 0 must also be written to the U bit of that entry. The
write-back to memory is performed in the order of H'0, H'4, H'8, H'C, which are the lower four
bits of the address.
(3) Address-Array Write (Associative Operation)
When writing with the associative bit (A bit) in the address field set to 1, the addresses in the four
ways for the entry specified by the address field are compared with the tag address that is specified
by the data field. Write the U bit (only for operand cache) and the V bit specified by the data field
to the entry of the way that has a hit. However, the tag address and LRU bits remain unchanged.
When there is no way that has a hit, nothing is written and there is no operation. This function is
used to invalidate a specific entry in the cache.
When the U bit of the entry that has had a hit is 1 in the operand cache, writing back should be
performed. However, when 0 is written to the V bit, 0 must also be written to the U bit of that
entry. The write-back to memory is performed in the order of H'0, H'4, H'8, H'C, which are the
lower four bits of the address.
9.4.2 Data Array
To access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for
write accesses) must be specified. The address field specifies information for selecting the entry to
be accessed; the data field specifies the longword data to be written to the data array.
Specify the entry address for selecting the entry, the L bit indicating the longword position within
the (16-byte) line, and the W bit for selecting the way. In the L bit, B'00 is longword 0, B'01 is
longword 1, B'10 is longword 2, and B'11 is longword 3. In the W bit, B'00 is way 0, B'01 is way
1, B'10 is way 2, and B'11 is way 3. Since the access size of the data array is fixed at longword,
specify B'00 for bits 1 and 0 of the address.
Refer to figure 9.4 regarding the address and data format.
The following two operations are possible for the data array. Information in the address array is
not modified by this operation.
Rev. 1.00 Mar. 25, 2008 Page 259 of 1868
REJ09B0372-0100