SH7205 Datasheet, PDF (1347/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 AT Attachment Packet Interface (ATAPI)
(7) DMA start address register (ATAPI_DMA_START_ADR)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
DSTA[28:16]
Initial value: ^-
-
-
-
-
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DSTA[15:2]
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
Initial
Bit
Bit Name Value
R/W Description
31 to 29 

R
Reserved
28 to 2 DSTA[28:2] H'x000000 R/W
These bits specify a DMA start address, which is a
transfer start address for data in memory. Bits 28 to 0
are used to specify a DMA start address on a byte
basis.
Bits 1 and 0 are ignored because it is necessary to
secure a 32-bit address boundary for the DMA start
address.
[Write]
Write 1 to bits 28 and 27.
1, 0


R
Reserved
Notes: 1. This address will not change even after DMA becomes active; it will retain its setting.
2. The access destination is in SDRAM.
Rev. 1.00 Mar. 25, 2008 Page 1315 of 1868
REJ09B0372-0100