SH7205 Datasheet, PDF (481/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
(2) DMA Active Output Signal (DACT, i = 0 to 3)
If DMA transfer is in response to the DREQi request from an external pin and the read or write
destination is normal space (CS0 to CS5), the DMA active signal (DACTi) can be output to
outside the LSI. If the access destination is LSI interior or SDRAM space, the DACTi signal is not
output.
• To read from normal space by DMA, set the source DMA-active signal output control bit
(SACT) of the DMA mode register (DMMODn) to 1. DACTi is output when normal space is
read by DMA. For the DACTi output timing, see section 10, Bus State Controller (BSC). If
SACT is cleared to 0, DACTi is not output when normal space is read by DMA.
• To write to normal space by DMA, set the destination DMA-active signal output control bit
(DACT) of the DMA module register (DMMODn) to 1. DACTi is output when normal space
is written by DMA. See section 10, Bus State Controller (BSC). If DACT is cleared to 0,
DACTi is not output when normal space is written by DMA.
• If both SACT and DACT are set to 1 in DMA transfer from one normal space to another,
DACTi is output when normal space is read or written by DMA.
(3) DMA Acknowledge Output Signal (DACKi, i = 0 to 3)
If DMA transfer is performed in response to the DREQi request from an external pin, the DMA
acknowledge signal (DACKi) is output. DACKi is output with the same timing as DMAACK_N
that is the DMA acknowledge signal in the LSI.
Note:
The DACKi signal indicates the DMA operation timing in the LSI. If normal space or
SDRAM space is written by DMA, DMA write access observed outside the LSI may be
delayed several cycles compared with DMA write access in the LSI. In this case, DMA
write access may be observed outside the LSI after DACKi is negated.
Rev. 1.00 Mar. 25, 2008 Page 449 of 1868
REJ09B0372-0100