SH7205 Datasheet, PDF (623/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
TGRA_3
TCDR
Bit WRE = 1
Synchronous clearing
TGRB_3
TCNT_3
(MTU2)
TDDR
TCNT_4
(MTU2)
H'0000
Positive phase
Negative phase
Output waveform is active-low.
Initial value output is suppressed.
Figure 12.61 Example of Synchronous Clearing in Interval Tb at Trough
(Timing (11) in Figure 12.56; Bit WRE of TWCR is 1)
Rev. 1.00 Mar. 25, 2008 Page 591 of 1868
REJ09B0372-0100