SH7205 Datasheet, PDF(832/1904 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SH7205 Datasheet, PDF (832/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

◁

Section 17 Synchronous Serial Communication Unit (SSU)

Figure 17.1 shows a block diagram of the SSU.

Module data bus

Peripheral bus

SSTDR 0

SSTDR 1

SSTDR 2

SSTDR 3

SSRDR 0

SSRDR 1

SSRDR 2

SSRDR 3

SSCRH

SSCRL

SSCR2

SSMR

SSER

SSSR

Control circuit

SSERI

SSRXI

SSTXI

SSTRSR

Selector

Clock

Clock

selector

PÏ

PÏ/4

PÏ/8

PÏ/16

PÏ/32

PÏ/64

PÏ/128

PÏ/256

SSI

SSO

SCS

[Legend]

SSCRH:

SS control register H

SSCRL:

SS control register L

SSCR2:

SS control register 2

SSMR:

SS mode register

SSER:

SS enable register

SSSR:

SS status register

SSTDR0 to SSTDR3: SS transmit data registers 0 to 3

SSRDR0 to SSRDR3: SS receive data registers 0 to 3

SSTRSR:

SS shift register

SSCK (External clock)

Figure 17.1 Block Diagram of SSU

Rev. 1.00 Mar. 25, 2008 Page 800 of 1868

REJ09B0372-0100

▷