SH7205 Datasheet, PDF (425/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
Bit
25, 24
Initial
Bit Name Value
DSEL[1:0] 00
23 to 18 
All 0
17, 16 STRG[1:0] 00
15 to 12 
All 0
R/W Description
R/W DMA Transfer Condition Select
These bits are used to set DMA transfer conditions.
Setting these bits to 00 selects unit operand transfer. Setting
these bits to 01 selects sequential operand transfer. Setting
these bits to 11 selects non-stop transfer (for details, see
section 11.4.2, DMA Transfer Conditions).
Do not set these bits to 10. Operation is not guaranteed if
this setting is made.
00: Unit operand transfer
01: Sequential operand transfer
10: Setting prohibited
11: Non-stop transfer
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Input Sense Mode Select
These bits are used to set input sense mode for the DMA
request signal to be input to the DMAC from the request
source selected by the DMA request source select bit
(DCTG). Table 11.8 shows the relationship between DMA
request sources and input sense modes. If the software
trigger (DCTG = 000000) is selected as the request source,
set rising edge sense. If the DREQ pins (DCTG = 000001 to
000100) are selected, any input sense mode can be
selected. If other request sources are selected, be sure to
set low level sense.
00: Rising edge sense
01: High level sense
10: Falling edge sense
11: Low level sense
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 393 of 1868
REJ09B0372-0100