SH7205 Datasheet, PDF (295/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Section 10 Bus State Controller (BSC)
The bus state controller (BSC) outputs control signals for external devices and various types of
memory that is connected to the external address space. This enables the LSI to connect directly
with SRAM, SDRAM, and other memory storage devices, and external devices.
10.1 Features
1. External address space
 Maximum of 64 Mbytes for the SDRAM and each for areas CS0 to CS5
 Ability to select the data bus width (8, 16, or 32 bits) independently for each address space
2. Normal space interface
 Supports an interface for direct connection to SRAM
 Cycle wait function: Maximum of 31 wait states (maximum of seven wait states for page
access cycles)
 Wait control
Ability to select the assert/negate timing for chip select signals
Ability to select the assert/negate timing for the read strobe and write strobe signals
Ability to select the data output start/end timing
Ability to select the delay for chip select signals
 Write access modes: One-write strobe and byte-write strobe modes
 Page access mode: Support for page read and page write (64-bit, 128-bit, and 256-bit page
units)
3. SDRAM interface
 Ability to set SDRAM in up to two areas
 Refresh functions
Auto-refresh (on-chip programmable refresh counter)
Self-refresh
 Ability to select the access timing (support for row-column latency, column latency, and
row-active interval settings)
 Initialization sequencer function, power-down function, deep-power-down function, and
mode register setting function implemented on-chip
Rev. 1.00 Mar. 25, 2008 Page 263 of 1868
REJ09B0372-0100