SH7205 Datasheet, PDF (411/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value
R/W Description
31 to 26 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
25 to 0 CBC[25:0] Undefined R/W Number of bytes to be transferred by DMA
Notes: 1. Note that when the value in this register is H'000 0000, 64M bytes (maximum number of
bytes to be transferred) are transferred.
2. Set this register so that the byte count becomes 0 as follows when the final data is sent
in a DMA transfer:
• When the transfer data size is set to 16 bits (SZSEL = 001): (bit 0) = 0
• When the transfer data size is set to 32 bits (SZSEL = 010): (bit 1, bit 0) = (0, 0)
3. Only write data to this register when the corresponding channel is not undergoing single
operand transfer (the DASTS bit of the corresponding channel in the DMA arbitration
status register (DMASTS) is 0) and DMA transfer is disabled (the DMST bit of the DMA
activation control register (DMSCNT) is 0 or the DEN bit of DMA control register B
(DMCNTBn) is 0). In other cases, operation is not guaranteed when data is written to
this register.
Rev. 1.00 Mar. 25, 2008 Page 379 of 1868
REJ09B0372-0100