SH7205 Datasheet, PDF (170/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Exception Handling
Exception Handling
Timing of Source Detection and Start of Handling
Instructions
FPU exception
Starts upon detection of invalid operation exception defined by
IEEE standard 754, division-by-zero, overflow, underflow, or
inexact exception. Also starts when qNaN or ±∞ is input to the
source for a floating point operation instruction when the QIS bit in
FPSCR is set.
When exception handling starts, the CPU operates as follows:
(1) Exception Handling Triggered by Reset
The initial values of the program counter (PC) and stack pointer (SP) are fetched from the
exception handling vector table (PC and SP are respectively at the H'00000000 and H'00000004
addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets).
See section 6.1.3, Exception Handling Vector Table, for more information. The vector base
register (VBR) is then initialized to H'00000000, the interrupt mask level bits (I3 to I0) of the
status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are initialized to 0. The
BN bit in IBNR of the interrupt controller (INTC) is also initialized to 0. The program begins
running from the PC address fetched from the exception handling vector table.
(2) Exception Handling Triggered by Address Errors, Sleep Errors, Register Bank Errors,
Interrupts, and Instructions
SR and PC are saved to the stack indicated by R15. In the case of interrupt exception handling
other than NMI or UBC with usage of the register banks enabled, general registers R0 to R14,
control register GBR, system registers MACH, MACL, and PR, and the vector table number of the
interrupt exception handling to be executed are saved to the register banks. In the case of
exception handling due to an address error, sleep error, register bank error, NMI interrupt, UBC
interrupt, or instruction, saving to a register bank is not performed. When saving is performed to
all register banks, automatic saving to the stack is performed instead of register bank saving. In
this case, an interrupt controller setting must have been made so that register bank overflow
exceptions are not accepted (the BOVE bit in IBNR of the INTC is 0). If a setting to accept
register bank overflow exceptions has been made (the BOVE bit in IBNR of the INTC is 1),
register bank overflow exception will be generated. In the case of interrupt exception handling, the
interrupt priority level is written to the I3 to I0 bits in SR. In the case of exception handling due to
an address error, sleep error, register bank error, or instruction, the I3 to I0 bits are not affected.
The start address is then fetched from the exception handling vector table and the program begins
running from that address.
Rev. 1.00 Mar. 25, 2008 Page 138 of 1868
REJ09B0372-0100