SH7205 Datasheet, PDF (462/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
(3) DMA Activation Sources and Restrictions
When the DMAC is activated by an on-chip peripheral module, the transfer source, transfer
destination, operand size, data size, transfer conditions, and transfer mode (whether pipelined
transfer is available) may be fixed. Table 11.11 shows the transfer methods that can be selected for
each DMA request source.
Table 11.11 Transfer Methods That Can Be Selected in Each DMA Request Source
Request Source
Software trigger
DREQ0 pin
DREQ1 pin
DREQ2 pin
DREQ3 pin
USB_0
USB_1
CMT_0
CMT_1
CMT_2
CMT_3
MTU2_0
MTU2_1
MTU2_2
MTU2_3
MTU2_4
IIC3_0 reception
IIC3_1 reception
IIC3_2 reception
IIC3_3 reception
Transfer
Source
No restriction
No restriction
Transfer
Destination
No restriction
No restriction
Operand
Size
(OPSEL)
No
restriction
No
restriction
Data Size
(SZSEL)
Transfer Piepelined
Condition Transfer
(DSEL)*¹ (MDSEL)
No
No
Available
restriction restriction
No
No
Available
restriction restriction
Write:
No restriction
Read: D0FIFO,
D1FIFO
No restriction
Write: D0FIFO, *²
D1FIFO
Read:
No restriction
No restriction No
restriction
*²
No
restriction
Unit
No
restriction
Not
available
Available
No restriction
No restriction No
No
No
Available
restriction restriction restriction
ICDRR_0
No restriction 1
8
Unit
Not
ICDRR_1
available
ICDRR_2
ICDRR_3
Rev. 1.00 Mar. 25, 2008 Page 430 of 1868
REJ09B0372-0100