SH7205 Datasheet, PDF (354/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
(7) Power-Down Mode
SDRAMC supports power-down mode for SDRAM. In power-down mode, it drives the CKE
signal low. In power-down mode, auto-refresh operations are performed at the intervals specified
by the auto-refresh request interval setting (DRFC) bits in SDRAM refresh control register 1
(SDRFCNT1). The CKE signal goes high only when an auto-refresh command is issued.
To perform transition to and recovery from power-down mode, use the SDRAM power-down
control register (SDPWDCNT).
Setting the DPWD bit to 1 causes SDRAMC to enter power-down mode. Clearing the DPWD bit
to 0 causes SDRAMC to exit power-down mode.
SDRAMC drives the CKE signal high after recovery from power-down mode.
CKIO
CKE
SDRAMC power-down mode
Figure 10.12 SDRAMC Power-Down Mode
SDRAMC power-down mode
CKIO
CKE
RFA
Auto-refresh command
Figure 10.13 Auto-Refresh Operation in SDRAMC Power-Down Mode
Rev. 1.00 Mar. 25, 2008 Page 322 of 1868
REJ09B0372-0100