SH7205 Datasheet, PDF (408/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.1 DMA Current Source Address Registers (DMCSADRn)
DMCSADRn is a register used to specify the start address of the transfer source. The value in this
register is transferred to the working source-address register when DMA transfer starts. The
contents of the working source-address register are returned to this register when an operand
transfer is completed. If the rotate setting (SAMOD = 011) is made for the source address,
however, the contents of the working source-address register are not returned. If the source-
address reload function is enabled, the contents stored in the DMA reload source address register
(DMRSADRn) are returned to this register when DMA transfer is completed. This register must
be set regardless of whether the reload function is enabled or disabled.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSA[31:16]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CSA[15:0]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Initial
Bit Name Value
R/W
CSA[31:0] Undefined R/W
Description
Holds source address bits A31 to A0.
Notes: 1. Set this register so that DMA transfer is performed for the following selected transfer
data sizes within the correctly arranged address boundaries:
• When the transfer data size is set to 16 bits (SZSEL = 001): (bit 0) = 0
• When the transfer data size is set to 32 bits (SZSEL = 010): (bit 1, bit 0) = (0, 0)
2. Only write data to this register when the corresponding channel is not undergoing single
operand transfer (the DASTS bit of the corresponding channel in the DMA arbitration
status register (DMASTS) is 0) and DMA transfer is disabled (the DMST bit of the DMA
activation control register (DMSCNT) is 0 or the DEN bit of DMA control register B
(DMCNTBn) is 0). In other cases, operation is not guaranteed when data is written to
this register.
Rev. 1.00 Mar. 25, 2008 Page 376 of 1868
REJ09B0372-0100