SH7205 Datasheet, PDF (1144/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
(2) Continuous Sector Access
A series of sectors can be read or written by specifying the start sector address of NAND-type
flash memory and the number of sectors to be transferred. Figure 23.16 shows an example of
physical sector specification register and transfer count specification register settings when
transferring logical sectors 0 to 40, which are not contiguous because of an unusable sector in
NAND-type flash memory.
Physical Logical
sector sector
0
0
11
11
12
13
13
40
40
300
12
Values specified in registers by the CPU.
Physical sector Sector transfer count
specification
specification
(ADR[17:0] in FLADR) (SCTCNT in FLCMDCR) _{Transfer start}
00
12
Sector 0 to sector 11 are transferred
300
1
Transfer start
Sector 12 is transferred
13
28
Transfer start
Sector 13 to sector 40 are transferred
Figure 23.16 Sector Access when Unusable Sector Exists in Continuous Sectors
23.4.6 ECC Error Correction
The FLCTL generates and adds ECC during write operation in sector access mode and performs
ECC error check during read operation in sector access mode. ECC processing is selectable
between 3-symbol ECC, the function provided in the earlier FLCTL, and 4-symbol ECC.
With 3-symbol ECC, only ECC generation and error detection are performed and error correction
is not performed. So, errors must be corrected by software. On the other hand, 4-symbol ECC is
capable of ECC generation, error detection, and error correction pattern generation by hardware.
Rev. 1.00 Mar. 25, 2008 Page 1112 of 1868
REJ09B0372-0100