SH7205 Datasheet, PDF (473/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
• Edge sense setting (falling edge sense)
CKIO
DREQ0 to DREQ3
DMA request bit
The DMA request bit is
set via valid edge input.
The DMA request bit is retained even if
the DMA request input level changes.
• Level sense setting (low level sense)
CKIO
DREQ0 to DREQ3
DMA request bit
The DMA request bit is set
when the active level is sampled
at the end of two clock periods.
[Legend]
: Sampling point for DMA request signal
The DMA request bit is cleared
when the inactive level is sampled.
Figure 11.7 Example of DMA Request Bit Timing for DMA Request Signal Input
Rev. 1.00 Mar. 25, 2008 Page 441 of 1868
REJ09B0372-0100