SH7205 Datasheet, PDF (1315/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
• This is applicable when the CURPIPE bits for CFIFO have the DCP setting (000).
Start
[1]
Set the ISEL bits to 1.
[1] Selects writing as the direction.
[2] Set the MBW bits as desired, and the ISEL bits to select reading as
the direction.
Read the ISEL bits to confirm
that the written value and the read
value are the same.
[2]
Set bits MBW and ISEL
at the same time.
Read the ISEL bits to confirm
that the written value and the read
value are the same.
End of adjusting the MBW bits
Figure 24.13 Example of Adjusting the MBW Bits when the CURPIPE Bits of CFIFO have
a DCP Setting (000)
(4) DMA Transfer (D0FIFO, D1FIFO Ports)
(a) Overview of DMA Transfer
For pipes 1 to 9, the FIFO port is accessible by the DMAC. When the buffer to the pipe set for
DMA becomes accessible, a DMA transfer request is output.
In the DnFIFOSEL register, use the MBW bits to set the unit of transfer to the FIFO port for the
pipe set for DMA transfer by the CURPIPE bits. Do not change the pipe number while DMA
transfer is enabled.
(b) Automatic Recognition of Completion of DMA Transfer
In this module, completion of the writing of FIFO data by DMA transfer can be under the control
of the input of a DMA transfer end signal. Then DMA transfer end signal causes the DMAC to
proceed with DMA transfer the number of times that corresponds to the setting of the DMA
current byte count register (DMCBCT) in the DMAC. Transfer to the buffer memory is enabled
(the same as setting BVAL = 1) when the DMA transfer end signal is sampled. The setting for
sampling or non-sampling of the DMA transfer end signal can be made in the TENDE bit of the
DnFBCFG register. Furthermore, be sure to set the DMA transfer end signal output control bits
Rev. 1.00 Mar. 25, 2008 Page 1283 of 1868
REJ09B0372-0100