SH7205 Datasheet, PDF (931/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
19.3.3 Transmit Data Register (SSITDR)
SSITDR is a 32-bit register that stores data to be transmitted. The data for transmission to be
stored to SSITDR is automatically transferred from the FIFO data register.
Data written to this register is transferred to the shift register upon transmission request. If the data
word length is less than 32 bits, the alignment is determined by the setting of the PDTA control bit
in SSICR.
The CPU cannot read or write data from/to SSITDR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: ^-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
19.3.4 Receive Data Register (SSIRDR)
SSIRDR is a 32-bit register that stores received data. The received data stored in SSIRDR is
automatically transferred to the FIFO data register.
Data in this register is transferred from the shift register each time data word is received. If the
data word length is less than 32 bits, the alignment is determined by the setting of the PDTA
control bit in SSICR.
The CPU cannot read or write data from/to SSIRDR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Rev. 1.00 Mar. 25, 2008 Page 899 of 1868
REJ09B0372-0100