SH7205 Datasheet, PDF (163/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Clock Pulse Generator (CPG)
5.5.3 Notes on Changing the Multiplication Rate and Division Ratio
1. When the division ratio for the CPU1 internal clock is changed, if IFC[1:0] of FRQCR1 are
changed while CPU1 is in the sleep state, the change is not reflected. To prevent malfunction,
always change the FRQCR1 register from CPU1.
2. When the multiplication rate or division ratio is changed through the frequency control
registers 0 and 1 (FRQCR0 and FRQCR1) while the DMAC is transferring data, the DMA
transfer is not guaranteed because the frequency is changed without waiting for the completion
of the DMA transfer. Therefore, to change the multiplication rate or division ratio through the
frequency control registers 0 and 1 (FRQCR0 and FRQCR1), wait for the completion of the
DMA transfer or stop the DMA transfer and then change the frequency control registers 0 and
1 (FRQCR0 and FRQCR1).
Rev. 1.00 Mar. 25, 2008 Page 131 of 1868
REJ09B0372-0100