SH7205 Datasheet, PDF (437/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.12 DMA Common Interrupt Control Register (DMICNTA)
DMICNTA controls DMA interrupts for each channel.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN
TA0 TA1 TA2 TA3 TA4 TA5 TA6 TA7 TA8 TA9 TA10 TA11 TA12 TA13
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
31 to 18 DINTA0 H'0000 R/W DMA Common Interrupt Request Signal Control
to
DINTA13
These bits are used to determine which channels contribute to
the output of a common interrupt request signal. Only the
channels for which these bits are set to 1 are grouped into one
as the common interrupt request signal. The channels for which
these bits are cleared to 0 do not contribute to the output of a
common interrupt request signal. Also only the channels for
which these bits are set to 1 are reflected in the DMA interrupt
status register (DMISTS) when a common interrupt request
signal is generated (for details, see section 11.5.2, DMA
Interrupt Requests).
0: The channel is not involved in common interrupt request.
1: The channel is involved in common interrupt request.
17 to 0 
All 0 R Reserved
These bits are always read as 0. The write value should always
be 0.
Note: Bits 31 to 18 correspond to channels 0 to 13.
Rev. 1.00 Mar. 25, 2008 Page 405 of 1868
REJ09B0372-0100