SH7205 Datasheet, PDF (318/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
10.4.8 SDRAM Refresh Control Register 1 (SDRFCNT1)
SDRFCNT1 controls auto-refresh operation.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
- DRFEN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Bit: 15
Initial value: -
R/W: R/W
14 13
DREFW[3:0]
-
-
R/W R/W
12
-
R/W
11
-
R/W
10
-
R/W
9
-
R/W
8
-
R/W
7
-
R/W
6
5
DRFC[11:0]
-
-
R/W R/W
4
-
R/W
3
-
R/W
2
-
R/W
1
-
R/W
0
-
R/W
Bit
Bit Name
31 to 17 
16
DRFEN
Initial
Value R/W Description
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
0
R/W Auto-Refresh Operation Enable
This bit controls auto-refresh operation for all channels
simultaneously. When DRFEN is cleared to 0, auto-
refresh operation does not take place. Auto-refresh
operates when DRFEN is set to 1. Clearing this bit to 0
while auto-refresh is enabled causes the DRFEN bit to be
cleared to 0, and auto-refresh operation to halt, after the
end of the next auto-refresh cycle. Setting this bit to 1
while auto-refresh is disabled causes auto-refresh
operation to commence as soon as the DRFEN bit is set
to 1, and refresh requests are then generated at fixed
intervals determined by a counter. The interval at which
refresh requests are generated is determined by the set
value of the auto-refresh request interval setting (DRFC)
bits. Refresh requests are not accepted while SDRAM is
being accessed; they must wait until the access
completes. If an SDRAM access and refresh request are
generated at the same time, the refresh request takes
precedence.
0: Auto-refresh disabled
1: Auto-refresh enabled
Rev. 1.00 Mar. 25, 2008 Page 286 of 1868
REJ09B0372-0100