SH7205 Datasheet, PDF (224/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
(5) DREQER4
Initial
Bit Bit Name Value R/W Description
7
SCIF TXI3 0
R/W DMA Transfer Enable
6
SCIF RXI3 0
R/W These bits enable or disable DMA transfer requests and
5
SCIF TXI2 0
R/W ^{CPU interrupt requests.}
4
SCIF RXI2 0
R/W
0: DMA transfer request is disabled and CPU interrupt
request is enabled.
3
SCIF TXI1 0
R/W _{1: DMA transfer request is enabled and CPU interrupt}
2
SCIF RXI1 0
R/W
request is disabled.
1
SCIF TXI0 0
R/W
0
SCIF RXI0 0
R/W
(6) DREQER5
Initial
Bit Bit Name Value R/W Description
7, 6 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
5
SSI SSIRTI5 0
R/W DMA Transfer Enable
4
SSI SSIRTI4 0
R/W These bits enable or disable DMA transfer requests and
3
SSI SSIRTI3 0
R/W ^{CPU interrupt requests.}
2
SSI SSIRTI2 0
R/W
0: DMA transfer request is disabled and CPU interrupt
request is enabled.
1
SSI SSIRTI1 0
R/W _{1: DMA transfer request is enabled and CPU interrupt}
0
SSI SSIRTI0 0
R/W
request is disabled.
Rev. 1.00 Mar. 25, 2008 Page 192 of 1868
REJ09B0372-0100