SH7205 Datasheet, PDF (1416/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
26.3.28 Panel-Output Mixing Vertical Valid Area Setting Register for Output Block
(MGR_MIXVS)
The register MGR_MIXVS sets the vertical area for signal output to the panel. The register value
is applied in synchronization with the VSYNC signal. For details, see section 26.4.1 (5), Setting of
Panel Output.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
ALLPV
Initial value: -
-
-
-
-
-
-
0
0
0
0
0
1
1
0
1
R/W: R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14
-
-
Initial value: -
-
R/W: R
R
13 12
-
-
-
-
R
R
11 10
-
-
-
-
R
R
9
8
7
6
5
4
3
2
1
0
-
VLDPV
-
0
0
0
0
0
0
1
1
1
R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit name Value
R/W Description
31 to 25 
Undefined R
Reserved
The read value is undefined. The write value should
always be 0.
24 to 16 ALLPV
H'00D
R/W Panel Output VSYNCH Period Width
These bits set high-level period of VSYNC for panel
output using the number of lines.
Valid range: 0 to 511 lines
15 to 9 
Undefined R
Reserved
The read value is undefined. The write value should
always be 0.
8 to 0 VLDPV
H'007
R/W Panel Output Image Vertical Valid Width
These bits set the valid width of panel output image
in the vertical direction using the number of lines from
PDPV.
Valid range: 0 to 511 lines
Note: The settings in this register and in the source E read-in area for the output block (the
MGR_SESET register) must be the same
The VLDPV bits are equivalent to the SEHIGH bits in MGR_SESET.
Rev. 1.00 Mar. 25, 2008 Page 1384 of 1868
REJ09B0372-0100