SH7205 Datasheet, PDF (752/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 15 Realtime Clock (RTC)
15.3.17 RTC Control Register 2 (RCR2)
RCR2 is a register for periodic interrupt control, 30-second adjustment ADJ, divider circuit
RESET, and RTC count control.
RCR2 is initialized by a power-on reset or in deep standby mode. Bits other than the RTCEN and
START bits are initialized by a manual reset.
BIt: 7
6
5
4
3
2
1
0
PEF
PES[2:0]
RTCEN ADJ RESET START
Initial value: 0
0
0
0
1
0
0
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit Bit Name Value
7
PEF
0
6 to 4 PES[2:0] 000
R/W Description
R/W Periodic Interrupt Flag
Indicates interrupt generation with the period designated
by the PES2 to PES0 bits. When set to 1, PEF generates
periodic interrupts.
0: Interrupts not generated with the period designated by
the bits PES2 to PES0.
[Clearing condition]
When 0 is written to PEF
1: Interrupts generated with the period designated by the
PES2 to PES0 bits.
[Setting condition]
When an interrupt is generated with the period
designated by the bits PES0 to PES2 or when 1 is
written to the PEF flag
R/W Interrupt Enable Flags
These bits specify the periodic interrupt.
000: No periodic interrupts generated
001: Periodic interrupt generated every 1/256 second
010: Periodic interrupt generated every 1/64 second
011: Periodic interrupt generated every 1/16 second
100: Periodic interrupt generated every 1/4 second
101: Periodic interrupt generated every 1/2 second
110: Periodic interrupt generated every 1 second
111: Periodic interrupt generated every 2 seconds
Rev. 1.00 Mar. 25, 2008 Page 720 of 1868
REJ09B0372-0100