SH7205 Datasheet, PDF (1422/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
(2) Assignment of Pixels to the Memory Space
Input and output data are mapped on the memory space as shown in figure 26.4. This example
shows the data mapping in the case where the selected format is αRGB444 (16 bits).
Starting address
Target plane area
α0 R0
G0 B0
α1 R1
G1 B1
α2 R2
G2 B2
α3 R3
G3 B3
Base_addr + 0
Base_addr + 1
Base_addr + 2
Base_addr + 3
Base_addr + 4
Base_addr + 5
Base_addr + 6
Base_addr + 7
Base_addr + 8
Figure 26.4 Example of Data Mapping (for the αRGB444 (16 bit) Pixel Format)
(3) Relations between Line Pitches and Memory Plane
The target display panels for the 2DG are QVGA (320 pixels × 240 lines) and WQVGA (480
pixels × 234 lines). The line pitch that determines the relations between memory space and each
work screen (such as the character plane and graphics plane) of the SDRAM must be placed on the
64-byte boundaries. Thus, the start addresses of each planes become the following.
XXXX_XX [4n] [0] (H) (X = arbitrary number, n = integer)
So, the starting address must be one of these: XXXX_XX00, XXXX_XX40, XXXX_XX80, or
XXXX_XXC0.
Figure 26.5 shows an example of the relations between the arrangement of planes A, B, and C,
(WQVGA size) and the pitch of display lines in memory for the αRGB444 (16-bits) pixel format.
Rev. 1.00 Mar. 25, 2008 Page 1390 of 1868
REJ09B0372-0100