SH7205 Datasheet, PDF (27/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

24.4.4 FIFO Buffer ........................................................................................................ 1276
24.4.5 Control Transfers (DCP)..................................................................................... 1287
24.4.6 Bulk Transfers (PIPE1 to PIPE5)........................................................................ 1290
24.4.7 Interrupt Transfers (PIPE6 to PIPE9) ................................................................. 1290
24.4.8 Isochronous Transfers (PIPE1 and PIPE2) ......................................................... 1292
24.4.9 SOF Interpolation Function ................................................................................ 1297
24.5 Usage Notes ..................................................................................................................... 1298
24.5.1 Procedure for Setting the USB Transceiver ........................................................ 1298
Section 25 AT Attachment Packet Interface (ATAPI) ....................................1299
25.1 Features............................................................................................................................ 1299
25.2 Input/Output Pins ............................................................................................................. 1300
25.3 Register Description......................................................................................................... 1301
25.3.1 ATAPI Interface Registers.................................................................................. 1301
25.3.2 ATAPI Interface Control Register Map.............................................................. 1304
25.4 Operation ......................................................................................................................... 1319
25.4.1 Data Transfer Modes .......................................................................................... 1319
25.4.2 Initialization Procedure....................................................................................... 1320
25.4.3 PIO Transfer Mode Operation Procedure ........................................................... 1320
25.4.4 Multiword DMA Transfer Mode Operation Procedure ...................................... 1321
25.4.5 Ultra DMA Transfer Mode Operation Procedure ............................................... 1323
25.4.6 ATAPI Device Hardware Reset Procedure......................................................... 1325
25.5 DIRECTION Pin.............................................................................................................. 1326
25.6 Usage Note....................................................................................................................... 1326
Section 26 2D Graphics Engine (2DG) ...........................................................1327
26.1 Features............................................................................................................................ 1327
26.2 Input/Output Pins ............................................................................................................. 1329
26.3 Register Descriptions ....................................................................................................... 1330
26.3.1 Blit Function Setting Register for Graphics (GR_BLTPLY).............................. 1333
26.3.2 Mixing Function Setting Register for Graphics (GR_MIXPLY)........................ 1335
26.3.3 Operation Status Register for Graphics (GR_DOSTAT).................................... 1336
26.3.4 Interrupt Status Register for Graphics (GR_IRSTAT) ....................................... 1340
26.3.5 Interrupt Mask Control Register for Graphics (GR_INTMSK).......................... 1345
26.3.6 Interrupt Reset Control Register for Graphics (GR_INTDIS) ............................ 1348
26.3.7 DMAC-Request Control Register for Graphics (GR_DMAC)........................... 1351
26.3.8 Source A&B Read-In-Area Setting Register for Blitter (GR_SABSET)............ 1354
26.3.9 Destination C Write Area Setting Register for Blitter (GR_DCSET)................. 1356
26.3.10 Source E Read-In Area Setting Register for Output Block (MGR_SESET) ...... 1357
26.3.11 Pixel Format Setting Register for Graphics (GR_PIXLFMT) ............................ 1359
Rev. 1.00 Mar. 25, 2008 Page xxvii of xxxii