SH7205 Datasheet, PDF (415/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.7 _{DMA Mode Register (DMMODn)}
DMMODn controls the amount of data, unit data size selection, address direction, and various
signal outputs.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
OPSEL[3:0]
-
-
-
-
-
SZSEL[2:0]
Initial value: 0
0
0
0
-
-
-
-
0
0
0
0
0
-
-
-
R/W: R
R
R
R R/W R/W R/W R/W R
R
R
R
R R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
SAMOD[2:0]
-
DAMOD[2:0]
-
-
-
- SACT DACT DTCM[1:0]
Initial value: 0
-
-
-
0
-
-
-
0
0
0
0
-
-
-
-
R/W: R R/W R/W R/W R R/W R/W R/W R
R
R
R R/W R/W R/W R/W
Bit
Bit
Name
31 to 28 
Initial
Value
All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 383 of 1868
REJ09B0372-0100