SH7205 Datasheet, PDF (1285/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
15 to 10 
9
TRENB
Initial
Value
R/W
Undefined R
0
R/W
Description
Reserved
Undefined values are read from these bits. The write
value should always be 0.
Transaction Counter Enable*³
Enables or disables the transaction counter.
For the pipe in the receiving direction, setting this bit
to 1 after setting the total number of the packets to
be received in the TRNCNT bits allows this module
to control hardware as described below on having
received the number of packets equal to the set
value in the TRNCNT bits.
• In continuous transmission/reception mode
(CNTMD = 1), this module switches the FIFO
buffer to the CPU side even if the FIFO buffer is
not full on completion of reception.
• While SHTNAK is 1, this module modifies the PID
bits to NAK for the corresponding pipe on having
received the number of packets equal to the set
value in the TRNCNT bits.
• While BFRE is 1, this module asserts the BRDY
interrupt on having received the number of
packets equal to the set value in the TRNCNT
bits and then reading out the last received data.
0: The transaction counter is disabled.
1: The transaction counter is enabled.
Note: For the pipe in the transmitting direction, set
this bit to 0.
When the transaction counter is not used, set
this bit to 0.
When the transaction counter is used, set the
TRNCNT bits before setting this bit to 1. Set
this bit to 1 before receiving the first packet to
be counted by the transaction counter.
Rev. 1.00 Mar. 25, 2008 Page 1253 of 1868
REJ09B0372-0100